SHA
A family of cryptographic hash algorithms that maps arbitrary-length data to a fixed-length digest.
GLOSSARY
Terms that connect the lessons.
Use each definition as a bridge back to the articles where the idea matters.
PUF
A circuit that turns uncontrollable manufacturing variation into a chip-unique response.
AES
A symmetric block cipher that transforms 128-bit blocks through repeated rounds.
RTL
A clock-aware hardware description of registers, data paths, and control transfers.
IPC
Instructions completed per clock cycle; a key measure beyond frequency.
MLP
Memory-level parallelism: overlapping multiple outstanding memory operations.
HBM
Stacked DRAM connected through a very wide, short interface for high bandwidth.
TSV
A vertical electrical connection passing through a silicon die.
ABF
A fine-line build-up film used as dielectric material in advanced package substrates.
CXL
A coherent interconnect for expanding and pooling memory and accelerators.
ASIC
A chip optimized for a specific workload instead of general-purpose execution.
LLM
A large language model that generates text by repeatedly predicting the next token from context.
Token
The text unit used by a model after tokenization; it maps to a vocabulary id.
Attention
A mechanism that lets a token compare its query with keys from other tokens and combine their values.
KV Cache
Cached Key and Value tensors from previous tokens, reused during autoregressive decoding.
PKI
A public-key trust system built around identities, certificates, and signatures.
FIPS 140-3
A validation standard for the design and operation of cryptographic modules.
CRA
The EU Cyber Resilience Act: lifecycle cybersecurity requirements for products with digital elements placed on the Union market.
CoWoS
An advanced package integrating compute and memory through an interposer.