SEMICONDUCTOR TECHNOLOGY
HBM, advanced packaging, AI inference architecture, and the system-level tradeoffs behind modern chips.
A precise, example-led walkthrough of tokenization, position information, Query-Key matching, Value mixing, residual connections, and what the KV cache does and does not save during autoregressive decoding.
AI TECHNOLOGY A six-page classroom that starts with a simple question: how does an LLM keep writing one piece at a time? We begin with next-token prediction, then move into tokens, vectors, K/V notes, KV Cache, and the memory cost that appears when conversations get long.
A nine-page classroom that turns the EU Cyber Resilience Act into a product-readiness map: scope, reporting dates, product classes, Annex I duties, conformity assessment, CE marking, and the evidence a real team must keep.
A nine-page classroom on why two CPU cores with the same GHz can behave very differently. The factory metaphor walks through frequency, IPC, width, branch prediction, out-of-order execution, MLP, cache, prefetching, and ISA design.
A six-page classroom on the hidden bottleneck in AI inference: not enough data arriving at the compute units. It connects GPU, HBM, ASIC, CXL, DRAM, and near-memory compute as different ways to keep inference hardware fed.
A six-page classroom on the base die at the bottom of an HBM stack. It explains why the base die is more than wiring, how traditional DRAM repair changes in a 3D stack, and why repair can protect the value of the whole AI package.
A five-page classroom on why GPUs need HBM. It starts with a simple road-width problem, then explains GDDR limits, silicon interposers, TSV stacks, HBM3E, HBM4, and why bandwidth gains bring packaging and yield challenges.
A seven-page classroom on advanced packaging as the work of moving chips closer together. It compares CoWoS, silicon interposers, CoPoS, ABF substrates, and PCBs by the distance, density, bandwidth, and yield problems they solve.
