SEMICONDUCTOR TECHNOLOGY
HBM, advanced packaging, AI inference architecture, and the system-level tradeoffs behind modern chips.
Start with photo conversion to separate individual latency, batch speedup and service throughput. Worked examples explain parallel work, Amdahl, shared bottlenecks and cost, followed by the limits of AI workflows, RISC-V claims and demand rebound.
Twelve illustrated lessons explain data movement, reticle stitching, defect tolerance, local SRAM, dataflow, CSoft, CS-4, prefill and decode, and the trade-offs among Cerebras, GPU clusters, and hardwired inference.
Follow data stalls and conflicting cached copies to understand cache, MESI, snoops, and directories, then examine false sharing, memory ordering, and CXL's limits.
A ten-plate classroom on hardwired inference: why moving weights is expensive, how a 4-bit lookup-and-select teaching model works, and how to read HC1's public numbers without overclaiming.
A story-led walkthrough of tokens, Query-Key matching, Value mixing, the two memory walls, and what KV cache saves—and still has to read—during autoregressive decoding.
A six-page classroom that starts with a simple question: how does an LLM keep writing one piece at a time? We begin with next-token prediction, then move into tokens, vectors, K/V notes, KV Cache, and the memory cost that appears when conversations get long.
A nine-page classroom that turns the EU Cyber Resilience Act into a product-readiness map: scope, reporting dates, product classes, Annex I duties, conformity assessment, CE marking, and the evidence a real team must keep.
Two CPUs both say 3GHz. Why does one finish the same job sooner? Follow a factory's work orders to understand IPC, branch prediction, out-of-order execution, and memory waits, then learn what a specification sheet leaves out.
A six-page classroom on the hidden bottleneck in AI inference: not enough data arriving at the compute units. It connects GPU, HBM, ASIC, CXL, DRAM, and near-memory compute as different ways to keep inference hardware fed.
A six-page classroom on the base die at the bottom of an HBM stack. It explains why the base die is more than wiring, how traditional DRAM repair changes in a 3D stack, and why repair can protect the value of the whole AI package.
A five-page classroom on why GPUs need HBM. It starts with a simple road-width problem, then explains GDDR limits, silicon interposers, TSV stacks, HBM3E, HBM4, and why bandwidth gains bring packaging and yield challenges.
A seven-page classroom on advanced packaging as the work of moving chips closer together. It compares CoWoS, silicon interposers, CoPoS, ABF substrates, and PCBs by the distance, density, bandwidth, and yield problems they solve.
