CPU CLASSROOM
Why do equal clock rates deliver different speeds, and why can extra cores still wait? Learn through concrete CPU, data, and parallel-work examples, then choose Arm, RISC-V, or design electives. Unfinished lessons are marked Planned.
CPU CLASSROOM · COURSE MAP
Why does changing the CPU or adding cores fail to speed up the same job as expected? Follow MY Teacher and MY Robot to find where work waits and how cores and data cooperate. Each lesson explains a mechanism through concrete examples, including its costs and limits.
Start with the available single-core, multi-core, and cache lessons to build intuition. In the full plan, the first six lessons establish performance and parallel-work foundations. Then follow prerequisites into memory systems, Arm, or RISC-V. Planned entries have no article yet; you do not need to finish all 26 lessons before beginning.
1 → 2 → 3 → 4 → 5 → 6
Build a shared foundation from GHz to scheduling and measurement.
1、3 → 13 → 14 → 15 → 16
Lesson 16 also requires SIMD from lesson 4. You can take this branch early.
1、3 → 13 → 18 → 19 → 20／21
Add lessons 8 and 10 for lesson 20, or lesson 4 for lesson 21.
19 → 23 → 24 → 25 → 26
Continue the RISC-V branch with synchronous RTL basics; lesson 26 also needs lessons 6, 12, and 22.
26 LESSONS · 5 STAGES
22 conceptual and analytical lessons plus 4 design electives. Available lessons open directly; planned lessons will be developed individually, with titles and order subject to refinement.
STAGE 01 · 1–6
Begin with the CPU factory, explore single cores, multiple cores, SIMD, and SMT, then learn to measure fairly.
Why can CPUs at the same GHz perform so differently?
After this lesson: Separate frequency from IPC and explain width, prediction, out-of-order execution, and data stalls.
Prerequisites: No earlier lessons · Basic programming and instruction concepts
Read this lesson →Why does adding cores fail to scale performance proportionally?
After this lesson: Identify serial work, shared bottlenecks, and imbalance, then propose a measurable question.
Prerequisites: Lesson 1
Read this lesson →Why are eight cores only four times faster at processing photos?
After this lesson: Compare schedules on a timeline, calculate speedup and parallel efficiency, and check correctness.
Prerequisites: Lesson 1, Lesson 2
This planned lesson will compare work decomposition, uneven finishing times, coordination, and combining results correctly. The outline’s 80 → 23 → 20 second example is a teaching model, not a benchmark.
What does eight cores and sixteen threads actually mean?
After this lesson: Explain shared execution resources and the tradeoff between hiding stalls and contention.
Prerequisites: Lesson 1
STAGE 02 · 7–12
Follow where data lives and how it is read, then examine handoffs between cached copies. Connect memory ordering, distance, and energy cost to decisions about the same job.
How do cores keep their cached copies coherent?
After this lesson: Trace cache-line reads, writes, and ownership through MESI, directories, and false sharing.
Prerequisites: Lesson 1, Lesson 7
This lesson is available and occupies position 9 in the full curriculum. Begin with cached copies and write-permission handoffs, then revisit the prerequisites when data-layout questions arise.
Read this lesson →STAGE 03 · 13–17
Separate instruction rules from implementations, explore Arm profiles, A64, and vectors, then examine x86 instruction decoding.
Why do Cortex-A, R, and M serve different needs?
After this lesson: Identify A/R/M profiles and their uses while separating architecture from implementation.
Prerequisites: Lesson 13
STAGE 04 · 18–22
Move from the open standard to programs, privileged systems, and vectors, then ask how the same software crosses platforms.
Does an open ISA mean an open or free chip?
After this lesson: Distinguish the base ISA, extensions, profiles, implementation licensing, and product costs.
Prerequisites: Lesson 13
STAGE 05 · 23–26
Build a teaching-subset CPU, add a pipeline, verify it, and evaluate design tradeoffs. Readers without RTL experience can begin with paper exercises.
How does an instruction drive the datapath and control signals?
After this lesson: Draw the PC, ALU, registers, and control FSM for an explicit teaching subset, not a complete RV32I implementation.
Prerequisites: Lesson 19 · Hands-on work also requires synchronous RTL, valid/ready, and testbench basics
Why can overlapping instructions read stale values?
After this lesson: Identify RAW hazards and reason about forwarding, stalls, flushes, and memory backpressure.
Prerequisites: Lesson 23
With one budget, should you add cores, cache, or improve software?
After this lesson: Evaluate workload, latency, throughput, and energy while separating teaching models from measurements.
Prerequisites: Lesson 6, Lesson 12, Lesson 22 · The RTL route also requires lesson 25
Start with photo conversion to separate individual latency, batch speedup and service throughput. Worked examples explain parallel work, Amdahl, shared bottlenecks and cost, followed by the limits of AI workflows, RISC-V claims and demand rebound.
Follow data stalls and conflicting cached copies to understand cache, MESI, snoops, and directories, then examine false sharing, memory ordering, and CXL's limits.
Two CPUs both say 3GHz. Why does one finish the same job sooner? Follow a factory's work orders to understand IPC, branch prediction, out-of-order execution, and memory waits, then learn what a specification sheet leaves out.
