COURSE SERIES

RTL Anti-Tampering Design

A 16-lesson plan on registers, control flow, permission handoffs and evidence under a stated fault model.

16 published · 0 planned

Conceptual RTL anti-tampering illustration; not a precise circuit diagram

Course outline

  1. 01
    Published

    RTL Anti-Tampering Design Lesson 1: Why Correct RTL Can Still Be Unsafe

    Follow a permission decision to the accepted commit.

  2. 02
    Published

    RTL Anti-Tampering Design Lesson 2: Write a Fault Model You Can Test

    Specify targets, effects, timing, budget and trusted boundaries.

  3. 03
    Published

    RTL Anti-Tampering Design Lesson 3: Can You Trust a Register's Value?

    Compare parity, complementary encoding and ECC under stated faults.

  4. 04
    Published

    RTL Anti-Tampering Design Lesson 4: Multi-bit control signals: which value can release the request?

    Check strict decoding and upstream single points of failure.

  5. 05
    Published

    RTL Anti-Tampering Design Lesson 5: DMR, TMR and common failures: what do agreeing copies prove?

    Include voter faults and dependence between replicas.

  6. 06
    Published

    RTL Anti-Tampering Design Lesson 6: Counters and progress: consistent values can finish early

    Find counters that are consistent but wrong.

  7. 07
    Published

    RTL Anti-Tampering Design Lesson 7: FSM state encoding: distance protects only the stored state

    Check Hamming distance and synthesized encoding.

  8. 08
    Published

    RTL Anti-Tampering Design Lesson 8: FSM transitions and history: permission belongs to this transaction

    Distinguish legal states from authorized control flow.

  9. 09
    Published

    RTL Anti-Tampering Design Lesson 9: Shadow registers and secure CSRs: protect the whole update

    Protect the update, lock and commit protocol.

  10. 10
    Published

    RTL Anti-Tampering Design Lesson 10: Alerts and local response: did detection arrive before acceptance?

    Measure when detection actually prevents a commit.

  11. 11
    Published

    RTL Anti-Tampering Design Lesson 11: Reset, Clocks, CDC and Lifecycle

    Review startup, domain crossings and debug permissions.

  12. 12
    Published

    RTL Anti-Tampering Design Lesson 12: Secure Boot and Key Release

    Bind image, version and key permissions to the final decision.

  13. 13
    Published

    RTL Anti-Tampering Design Lesson 13: DFA, SIFA and Information Leakage

    Separate control safety from cryptographic leakage.

  14. 14
    Published

    RTL Anti-Tampering Design Lesson 14: RTL and Netlist Fault Campaigns

    Build reproducible campaigns and classify counterexamples.

  15. 15
    Published

    RTL Anti-Tampering Design Lesson 15: Calibrating Physical Fault-Injection Models

    Compare physical observations with the digital model.

  16. 16
    Published

    RTL Anti-Tampering Design Lesson 16: Design Review and Evidence Packages

    Report scope, coverage, counterexamples and unknowns.