Interactive experiment

Startup / CDC trace

A common teaching timeline orders events by step; it does not compare clk_sys and clk_dbg cycle numbers. Check_done appears at step 2. Source availability, destination observation, and acceptance are separate. This model does not simulate synchronizer latency or metastability.

Controls

This case produces check_done at teaching step 2 At this teaching step, the destination has observed synchronized check_donePermission teaching timeline step (not a clock-cycle index)

Teaching abstraction only; not RTL, CDC proof, STA, reset-tree, analog, or silicon evidence.

Static worksheetThe no-JavaScript worksheet uses a common teaching event order, not clock-cycle numbers from different domains. Permission at step 1 precedes check_done at step 2: the source is not yet available and weak policy accepts early. At step 2, the source is available, but acceptance must stay blocked until the destination has observed synchronized check_done. Only both conditions make acceptance eligible in this abstraction. An equal-step case does not model actual synchronization latency or prove CDC safety.